Publications
Education
Education and Diversity
P. Teller and A. Gates, Using the Affinity Research Group Model to Involve Undergraduate Students in Computer Science Research, Journal of Engineering Education, October 2001.
P. Teller and A. Gates, Applying the SSEAL Affinity Research Group Model to Computer Science Research Projects, Proceedings of the 2000 Frontiers in Education Conference (FIE 2000), Kansas City, MO, October 18-21, 2000.
A. Bernat, P. Teller, A. Gates, N. Delgado, and C. Kubo Della-Piana, Structuring the Student Research Experience, Proceedings of the Fifth Annual Conference on Innovation and Technology in Computer Science Education (ITiCSE), Helsinki, Finland, pp. 17-20, July 11-12, 2000.
Keynote Talk: A. Gates and P. Teller: Providing Educational Opportunities to Diverse Populations: Affinity Research Groups,
Consortium for Computing in Small Colleges, Eleventh Annual South
Central Conference, Texas A&M University-Corpus Christi, April
14-15, 2000.
A. Gates, P. Teller, A. Bernat, S. Cabrera, and C. Kubo Della-Piana, Cooperative Model for Orienting Students to Research Groups, Proceedings of the 1999 Frontiers in Education Conference (FIE 1999), San Juan, Puerto Rico, CD-ROM, November 1999.
A. Gates, P. Teller, A. Bernat, N. Delgado, and C. Kubo Della-Piana, Expanding Participation in Undergraduate Research Using the Affinity Group Model, Journal of Engineering Education, 88, 4, pp. 409-414, October 1999.
A. Gates and P. Teller, "Research in the Systems and Software Engineering Lab," looking .forward, IEEE Computer Society's Student Newsletter, 7, 1, 1999.
A. Gates, P. Teller, A. Bernat, N. Delgado, and C. Kubo Della-Piana, Meeting the Challenge of Expanding Participation in the Undergraduate Research Experience, Proceedings of the 1998 Frontiers in Education Conference, Tempe, Arizona, pp.1133-1138, November 4-7, 1998 (Best Paper Award).
Student Presentation: N. Delgado, D. Fox, and S. Medina (Advisors: A. Gates and P. Teller), Towards
an Electronic Framework Supporting Affinity Group Projects: Program
Coordination, Communication, and Common Goal Tool for Teams, talk at Rio Grande ACM Meeting, El Paso, TX, El Paso, TX, March 27, 1998.
A. Bernat, A. Gates, P. Teller, and S. Cabrera, Affinity Groups for Student Success in Computing, Proceedings of the 1997 ADMI Conference, Washington, DC, pp. 206-211, May 29-30, 1997.
Conference Presentation:
An Orientation to the Affinity Research Group Model (with A. Gates), The Eighth National Conference on College Teaching and Learning,
Jacksonville, FLA, April 1997.
Course Development and Delivery
P. Teller, M. Nieto, and S. Roach,
Combining Learning Strategies in a First Course in Computer Architecture, Proceedings
of the Workshop on Computer Architecture Education (WCAE 2003),
held in conjunction with The 30th International Symposium on Computer
Architecture and 2003 Federated Computing Research Conference, San
Diego, CA, pp. 41-48, June 2003.
Conference Presentation: P.
Teller, Using RATs (Readiness Assessment Tests) to Motivate Team
Learning: from a Computer Science Perspective, The Sun Conference on
Teaching and Learning, March 7-8, 2003.
Conference Presentation: P. Teller, M. Roach, M. Maxwell, and M. Nieto,
Combining Learning Strategies to Prepare Student for Upper-level Computer Science Courses, The Sun Conference on Teaching and Learning, March 8-9, 2002.
P. Teller, Experimental, Cooperative Labs in a First Course in Computer Architecture, Proceedings of the 1997 Frontiers in Education Conference (FIE 97), Pittsburgh, PA, November 1997.
P. Teller and T. Dunning, Mobil Robots Teach Machine Programming and Organization, Proceedings of Supercomputing `95, San Diego, CA, CD-ROM, December 1995.
Diversity and Outreach
P. Teller, " Expanding the Pipeline: Coalition to Diversity Computing (CDC)," Computing Research News, p. 2, November 2004
Research Booth: Building Bridges of Opportunity along the Rio Grande, with University of New Mexico, New Mexico Institute of Technology, and New Mexico State University to promote computation-based research at UTEP, SC2004, Pittsburgh, PA, November 2004.
P. Teller, CRN Pipeline article re: the Coalition to Diversity Computing, Computing Research News, October 2004.
P. Teller, R. Amezcua, and R. Acotsa, Top Gun: UTEP's p690, Proceedings of the IBM-Austin ACAS 2004 Conference, February 2004.
Invited Presentation: The Importance of Undergraduate Research Experiences and Higher Education - a Personal Perspective, Research Experience For Undergraduates Spring 2002 Reception, The University of Texas at El Paso, May 15, 2002.
Panel Member, Increasing the Enrollment of Women in Computer Science, 32nd SIGCSE, Technical Symposium on Computer Science Education, Charlotte, NC, February 21-25, 2001.
Computer Science
POEMS, Performance Oriented End-to-end Modeling System
V. Adve, J. Browne, B. Ensink, J. Rice, P.
Teller, M. Vernon, and S. Wright, An Approach to Optimizing Adaptive
Parabolic PDE Solvers for the Grid, Proceedings of the IPDPS 2003 NGS
Workshop, April 2003.
V. Adve, A. Akinsanmi, J. Browne, D. Buaklee, G.
Deng, V. Lam, T. Morgan, J. Rice, G. Rodin, P. Teller, G. Tracy, M.
Vernon, S. Wright, and J. Yi, Model-Based Control of Adaptive
Applications: An Overview, Proceedings of the IPDPS 2002 NGS Workshop,
April 2002.
V. Adve, J. Vetter, R. Bodik, D. Kerbyson, S. Sen, and P. Teller, Working
Group 3: Performance Specification and Control Languages, Report for
Workshop on Performance Engineering Technology Research Sponsored under
the NSF Next Generation Software (NGS) Program, February 28-March 1,
2002, Austin, TX.
G. Rybak, P. Teller, and R. Oliver, Identifying Application Performance Limitations associated with Microarchitecture Design, Proceedings of the Los Alamos Computer Science Institute Symposium 2001 (LACSI 2001), Santa Fe, NM, October 15-18, 2001. (Also shown under Microprocessor Performance.)
V. Adve, R. Bagrodia, J. Browne, E. Deelman, A.
Dube, E. Houstis, J. Rice, R. Sakellariou, D. Sundaram-Stukel, P.
Teller, and M. Vernon, POEMS: End-to-end Performance Design of Parallel Adaptive Computational Systems, IEEE Transactions on Software Engineering, November 2000.
E. Deelman, A. Dube, Y. Luo, R. Oliver, D.
Sundaram-Stukel, V. Adve, R. Bagrodia, J. Browne, E. Houstis, O.
Lubeck, J. Rice, P. Teller, and M. Vernon, POEMS: End-to-end Performance Design of Parallel, Adaptive Computational Systems, Proceedings of the First International Workshop on Software and Performance (WOSP), Santa Fe, NM, pp. 18-30, October 12-16, 1998.
Conference Poster: POEMS: Performance Oriented End-to-end Modeling of Highly Parallel Computer and Communication Systems, Supercomputing 97, San Jose, CA, November 1997.
DynaMICs, Dynamic Monitoring of Integrity Constraints
A. Gates and P. Teller, An Integrated Development of a Dynamic Software-fault Monitoring System, Journal of Integrated Design and Process Science, 4, 3, pp. 63-78, September 2000.
A. Gates and P. Teller, An Integrated Design of a Dynamic Software-fault Monitoring System, Proceedings of the Fourth World Conference on Integrated Design and Process Technology, Dallas, TX, June 2000.
P. Teller and A. Gates, Progress Towards a Comprehensive Knowledge-based Monitoring System for the Development and Evolution of Software, Proceedings
of the High Performance Computing and Communications
Program/Computational Aerosciences 2000 Workshop (HPCC/CAS Workshop), NASA Ames Research Center, February 15-17, 2000.
A. Gates and P. Teller, DynaMICs: an Automated and Independent Software-fault Detection Approach, Proceedings of the Fourth IEEE International Symposium on High-Assurance Systems Engineering Symposium (HASE 99), Washington, D.C., pp. 11-19, November 17-19, 1999.
Student Paper: L. Rauda (Advisors: A. Gates and P. Teller), A Parallel Discrete-event Simulation of a DynaMICs Snoopy Coprocessor System, Proceedings of the Thirteenth National Conference on Undergraduate Research, Rochester, NY, April 1999.
P. Teller, M. Maxwell, and A. Gates, Towards the Design of a Snoopy Coprocessor for Dynamic Software-fault Detection, Proceedings of the 1999 IEEE International Performance, Computing and Communications Conference (IPCCC 99), Scottsdale, AZ, pp. 310-317, February 1999.
Student Paper: M. Maxwell and L. Rauda (Advisors: P. Teller and A. Gates),
An Initial Design of a Coprocessor/Snoopy Hardware Integrity Constraint Monitoring Simulator,
Proceedings
of the ITEA Workshop, Modeling and Simulation (Establishing Seamless,
Distributed and Integrated Solutions to Real-World Problems), Las Cruces, NM, pp. 385-394, December 7-10, 1998 (Best Student Paper Award, $1000 Scholarship).
Sampled Event Traces
D.
Villa, M. Meswani, P. Teller, and B. Olszewski, “Profiling Memory
Subsystem Performance in an Advanced POWER Virtualization Environment,”
Proceedings of the Workshop on Operating System Interference on High Performance Applications, in conjunction with the 14th
International Conferences on Parallel Architectures and Compilation
Techniques (PACT05) Conference, sponsored by ACM and IEEE, September
18, 2005.
R. Portillo, D. Villa, P. J. Teller, and B. Olszewski, “Mining Performance Data From Sampled Event Traces,” Proceedings
of the 12th Annual Meeting of the IEEE/ACM International Symposium on
Modeling, Analysis, and Simulation of Computer and Telecommunication
Systems (MASCOTS 2004), October 2004; also in Proceedings of the Sixth Annual Austin Center for Advanced Studies Conference, February 24-25, 2005.
R. Portillo, D. Villa, P. Teller, and B. Olszewski, “Mining Performance Data from Sampled Event Traces,” Proceedings of the IBM-Austin ACAS 2005 Conference, February 2005.
D.
Villa, J. Acosta, P. J. Teller, B. Olszewski, and T. Morgan, “Memory
Performance Profiling via Sampled Performance Monitor Event Traces,” Proceedings of the 5th Los Alamos Computer Science Symposium (LACSI 2004), October 2004.
D.
Villa, J. Acosta, P. J. Teller, B. Olszewski, and T. Morgan, Memory
Performance Profiling via Sampled Performance Monitor Event Traces, to
appear in the
Proceedings of the 5th Los Alamos Computer Science Symposium (LACSI 2004), October 2004.
R. Portillo, D. Villa, P. J. Teller, and B. Olszewski, Mining Performance Data From Sampled Event Traces, to appear in the Proceedings
of the 12th Annual Meeting of the IEEE/ACM International Symposium on
Modeling, Analysis, and Simulation of Computer and Telecommunication
Systems (MASCOTS 2004), The Netherlands, October 2004.
D. Villa, J. Acosta, P. J. Teller, B. Olszewski, and T. Morgan, “A Framework for Profiling Multiprocessor Memory Performance,” Proceedings of the 10th International Conference on Parallel and Distributed Systems, July 2004.
D. Villa, J. Acosta, P. J. Teller, B. Olszewski, and T. Morgan, A Framework for Profiling Multiprocessor Memory Performance,
Proceedings of the 10th International Conference on Parallel and Distributed Systems, July 2004.
D. Villa, J. Acosta, T. Morgan, P. Teller, and B.
Olszewski, Memory Performance Profiling via Sampled Performance Monitor
Event Traces, Proceedings of the IBM-Austin ACAS 2004 Conference, February 2004.
T. Morgan, D. Villa, P. Teller, J. Acosta, and B.
Olszewski, L2-Cache Miss Profiling on the p690 for a Large-scale
Database Application, Proceedings of the IBM-Austin ACAS 2003 Conference, February 2003.
Program Counters
R.
Araiza, M. G. Aguilera, T. Pham, and P. Teller, "Towards a
Cross-Platform Microbenchmark Suite for Evaluating Hardware Performance
Counter Data," ACM Digital Library, Proceedings of the Richard Tapia Celebration of Diversity in Computing Conference 2005, sponsored by ACM, IEEE-Computer Society, and CRA, September 18, 2005.
Conference Poster: Hardware Performance Counters: Is What You See, What You Get? (with A. Bayona and M. Nieto), SC2003, Phoenix, AZ, November 2003.
S. Moore, D. Terpstra, K. London, P. Mucci, P. Teller, L. Salayandia, A. Bayona, and M. Nieto, PAPI Deployment, Evaluation, and Extensions, Proceedings of the DoD High Performance Computing Modernization Programs User Group Conference 2003, Bellevue, WA, June 2003.
M. Maxwell, P. Teller, L. Salayandia, and S. Moore, Accuracy of Performance Monitoring Hardware, Proceedings of the Los Alamos Computer Science Institute Symposium 2002 (LACSI 2002), Santa Fe, NM, October 2002.
M. Maxwell, S. Moore, P. Teller, Efficiency and Accuracy Issues for Sampling vs. Counting Modes of Performance Monitoring Hardware, Proceedings of the DoD High Performance Computing Modernization Programs User Group Conference 2002, June 2002.
W. Korn, P. Teller, and G. Castillo, Just How Accurate Are Performance Counters, Proceedings of the 2001 IEEE International Performance, Computing and Communications Conference (IPCCC 2001), Phoenix, AZ, pp. 303-310, April 4-6, 2001.
Unscheduled Traces Multiprogrammed Systems
R. Oliver and P. J. Teller, Generating Dynamically Scheduled Memory Address Traces, Proceedings of the 1998 IEEE International Performance, Computing, and Communications Conference (IPCCC 98), Tempe/Phoenix, AZ, pp. 245-250, February 16-18, 1998.
P. Teller, Unscheduled Traces and Shared-memory Multiprocessor Simulation, Proceedings of the International Conference on Parallel Processing (ICPP 95), pp. I159-162, August 1995.
P. Teller, MP Simulations via Unscheduled Traces, Calculateurs paralleles, 7, 1, pp. 9-25, April 1995.
P. Teller, "Unscheduled Traces and Shared-memory Multiprocessor Simulation," Transputers `94: Advanced Research and Industrial Applications, France, September 1994.
Multiprocessor Performance
Q. Xu and P. Teller, Unified vs. split TLBs and Caches in Shared-memory MP Systems, Proceedings of the International Parallel Processing Symposium (IPPS 95), Santa Barbara, CA, pp. 398-403, April 1995.
P. Teller and Q. Xu, Memory-based Multiprocessor Translation-lookaside Buffers: Multiple Paging Arenas vs. Large-size TLBs, Proceedings of the International Phoenix Conference on Computers and Communication (IPCCC 1994), Phoenix, AZ, pp. 47-53, April 1994.
P. Teller and A. Gottlieb, Locating Multiprocessor TLBs at Memory, Proceedings of the Twenty-seventh Hawaii International Conference on System Sciences (HICSS 94), pp. 554-563, January 1994 (Best Paper Award Nominee in Architecture Track).
G. Chen, A. Gottlieb, and P. Teller, Optimization Techniques for Directory-based Cache Coherence Protocols for Large-scale Multiprocessors, Parallel Computing: Trends and Applications, pp. 671-674. 1994.
G. Chen, A. Gottlieb, and P. Teller, "Optimization Techniques for Directory-based Cache Coherence Protocols for Large-scale Multiprocessors," Proceedings of Parallel Computing 93, Grenoble, France, September 1993.
P. Teller, Translation-lookaside Buffer Consistency, IEEE Computer, 23, 6, pp. 26-36, June 1990.
Invited workshop presentation: Performance Evaluation of TLB Consistency Schemes via Trace-driven Simulation,
ISCA `90 Workshop on Scalable Shared-Memory Architectures (in
connection with the Seventeenth International Symposium on Computer
Architecture), May 1990.
P. Teller, The Cost of TLB Consistency, Cache and Interconnect Architectures in Multiprocessors, edited by M. Dubois and S. Thakkar, Norwell, MA: Kluwer Academic Publishers, pp. 1-14,1990.
P. Teller, TLB Consistency in Highly-parallel Shared-memory Multiprocessors, Sequent Computer Systems, Inc., Beaverton, Oregon, March 1990.
Invited Workshop Presentation: "Consistency-ensuring TLB Management and its Scalability,"
ISCA `89 Workshop on Cache and Interconnect Architectures in
Multiprocessors (in connection with the Sixteenth International
Symposium on Computer Architecture), May 1989.
R. Kenner, R. Bianchini, S. Dickey, and P. Teller, A Compact Design for a Highly-parallel Shared-memory MIMD Computer, Proceedings of Compcon Spring 1989, Miami, FLA, pp. 264-269, February/March 1989.
R. Kenner, S. Dickey, and P. Teller, The Design of Processing Elements on a Multiprocessor System with a High-bandwidth, High-latency Interconnection Network, Proceedings of the Twenty-Second Hawaii International Conference on System Sciences, pp. 319-328, January 1989.
P. Teller, TLB Consistency in Highly-parallel Shared-memory Multiprocessors, IBM, T.J. Watson Research Center, Yorktown Heights, NY, April 1988.
P. Teller, R. Kenner, and M. Snir, TLB Consistency on Highly-parallel Shared-memory Multiprocessors, Proceedings of the Twenty-First Hawaii International Conference on System Sciences (HICSS 88), pp. 184-193, January 1988 (Best Paper Award Nominee).
P. Teller, TLB Consistency in Highly-parallel Shared-memory Multiprocessors," BBN Advanced Computers, Inc., Cambridge, Mass., December 1987.
J. Edler, A. Gottlieb, C. Kruskal, K. McAuliffe, L. Rudolph, M. Snir, P. Teller, and J. Wilson, Issues Related to MIMD Shared-memory Computers: the NYU Ultracomputer Approach, Proceedings of the 12th Annual International Symposium on Computer Architecture, pp. 126-135, June 1985.
Microprocessor Performance
G. Rybak, P. Teller, and R. Oliver, Identifying Application Performance Limitations associated with Microarchitecture Design, Proceedings of the Los Alamos Computer Science Institute Symposium 2001 (LACSI 2001), Santa Fe, NM, October 15-18, 2001. (Also shown above under POEMS.)
R. Oliver and P. Teller, Dynamic and Adaptive Cache Prefetch Policies, Proceedings of the 2000 IEEE International Performance, Computing and Communications Conference (IPCCC 2000), Phoenix, AZ, February 20-22, 2000.
R. Oliver and P. Teller, Are All Scientific Workloads Equal?, Proceedings of the 1999 IEEE International Performance, Computing and Communications Conference (IPCCC 99), Scottsdale, AZ, pp. 284-290, February 1999.
R. Oliver, W. McGregor, and P. Teller, Accurate Measurement of System Call Service Times for Trace-driven Simulation of Memory Hierarchy Designs, Proceedings of the 1998 IEEE International r. Performance, Computing, and Communications Conference (IPCCC 98), Tempe/Phoenix, AZ, pp. 239-244, February 16-18, 1998.
Related Work
P. Teller, R. Amezcua, and R. Acotsa, “Top Gun: UTEP’s p690,” Proceedings of the IBM-Austin ACAS 2004 Conference, February 2004.
A. Bernat and P. Teller, Concurrent/Distributed Computing Paradigm, CRC Handbook of Computer Science and Engineering, Second Edition, edited by Allen Tucker, Bob Stern, and Bob Noonan, et al., December 2003.
Student Paper: A. Caraveo (Advisor: P. Teller), Accuracy and Precision Issues in GIS Data Transfers, Proceedings of the 1997 ADMI Symposium on Computing at Minority Institutions, Washington, D.C., pp. 106-111, May 29-30, 1997.
Student Paper: M. Maxwell (Advisor: P. Teller), Using VTune to Identify Potential Pentium Pro Performance Bottlenecks, Proceedings of the 1997 ADMI Symposium on Computing at Minority Institutions, Washington, D.C., pp. 2-5, May 29-30, 1997.
S. Cooper and P. Teller, Configuring a Large LAN for TCP/IP, Appletalk, and IPX, Proceedings of the Twentieth Annual Conference on Local Area Networks, October 1995.
Parallel Architectures,
Los Alamos National Laboratory-sponsored workshops, Los Alamos National
Laboratory, Los Alamos, NM and University of New Mexico, Albuquerque,
NM, July 1995, July 1994, January 1994, July 1993, and October 1993.
P. Teller and H. Stone, "Parallel Simulation of Multiprocessor Caches," IBM Invention Disclosure, July 1992.
P. Teller, Common Memory Working Group Summary, Instrumentation for Future Parallel Systems, edited by M. Simmons, R. Koskela, and I. Bucher, Addison-Wesley Publishing Co., pp. 233-237, 1989.
DAiSES-Dynamic Adaptivity in Support of Extreme Scale (Dynamic Operating System Adaptations to Enhance Performance)
S.Seelam, J. Suresh Babu, and P. Teller, "Automatic I/O Scheduler Selection for Latency and Bandwidth Optimization, "Proceedings of the Workshop on Operating System Interface on High Performance Applications, in conjunction with the 14th International
Conferences on Parallel Architectures and Compilation Techniques
(PACT05) Conference, sponsored by ACM and IEEE, August 31, 2005.
S. Seelam, R. Romero, P.Teller, and B. Buros, "Enhancements to Linux I/O Scheduling," Proceedings of the Linux Sympusium, July 2005.
DAPLDS-Dynamic Adaptive Protein Ligand Docking System (Desktop Grid Performance)
M. Taufer, P. Teller, D. Anderson, and C. Brooks III, "Metrics for
Effective Resource Managements in Global Computing Environments," to
appear in the
Proceedings of the 1st IEEE International Conference on e-Science and Grid Technologies (eScience 2005), Melbourne, Australia, December 2005.